The present invention relates generally to a method of forming a wiring structure by using a via-first dual damascene method which is used for forming a multi-layer wiring structure and the like of a semiconductor device. More particularly, the present invention relates to a method of forming a wiring structure by using a via-first dual damascene method in which a development rate of a photo resist film is optimized.
As a method of forming wiring conductors having a multi-layer structure in a semiconductor integrated circuit device, there is known a damascene wiring technology. Among the damascene wiring technology, a dual damascene technology has merits of simplifying a manufacturing process and shortening a Turn-and-Around-Time (TAT), and of greatly reducing manufacturing costs of a semiconductor integrated circuit device. In the dual damascene technology, wiring trenches for forming upper layer wiring conductors and via holes or contact holes (hereafter, referred to as via holes including both of the via holes and contact holes) for forming vias or via conductors which couple the upper layer wiring conductors and lower layer wiring conductors or substrates are formed in an insulating film, and thereafter the wiring trenches and the via holes are filled at the same time with a metal material to form the upper layer wiring conductors and the via conductors at the same time. Especially, among the dual damascene method, a via-first dual damascene method in which via holes are formed before forming wiring trenches has the merit of reducing unevenness of a photo resist film in an etching process for forming the via holes. Thereby, it becomes possible to perform minuter work of the dual damascene structure. As the photo resist, there are known a positive type photo resist and a negative type photo resist. In the dual damascene method, the positive type photo resist is generally used, because the positive type photo resist has high image resolution and many kinds of positive type photo resist materials are available.
With reference to the drawings, an explanation will be made on an example of a method of forming wiring conductors according to a conventional via-first dual damascene method. FIGS. 11A-11C, FIGS. 12A-12C and FIGS. 13A-13C are cross sectional views each illustrating a structure of a workpiece during a process of fabricating a dual damascene structure according to the conventional via-first dual damascene method.
First, as shown in FIG. 11A, an etching stopper film 7 made of SiCN is formed on a lower wiring layer 8. Then, an interlayer insulating film 6 made of SiO2 is formed on the etching stopper film 7, and an etching stopper film 5 made of SiC is formed on the interlayer insulating film 6. Further, an interlayer insulating film 4 made of ladder oxide is formed on the etching stopper film 5, and SiO2 is plasma deposited on the interlayer insulating film 4, thereby a cap film 3 is formed.
Then, a bottom anti-reflective coating (BARC) not shown in the drawing is applied on the cap film 3, and further a photo resist film not shown in the drawing is applied thereon. The photo resist film is then exposed by using KrF (krypton fluoride) excimer laser, and thereafter developed. Thereby, a via hole pattern is formed by a photolithography technology.
As shown in FIG. 11B, by using the photo resist film (not shown in the drawing) in which the via hole pattern is formed as a photo mask, the bottom anti-reflective coating (not shown in the drawing), the cap film 3, the interlayer insulating film 4, the etching stopper film 5 and the interlayer insulating film 6 are etched, thereby a via hole 9 reaching the etching stopper film 7 is formed. In the drawing, only one via hole 9 is shown. However, it is also possible to form many via holes at the same time. Thereafter, by using O2 plasma ashing and organic remover, the photo resist film and the bottom anti-reflective coating are removed.
Next, as shown in FIG. 11C, another bottom anti-reflective coating 2 made of organic material is formed on the cap film 3 and within the via hole 9. In this case, the bottom anti-reflective coating 2 is formed such that the via hole 9 is completely filled with the material of the bottom anti-reflective coating 2. That is, the via hole 9 is full-filled with the material of the bottom anti-reflective coating 2.
As shown in FIG. 12A, positive type photo resist material is applied on the bottom anti-reflective coating 2 and, thereby, a photo resist film 11 is formed on the bottom anti-reflective coating 2.
Then, as shown in FIG. 12B, the photo resist film 11 is exposed by using KrF excimer laser, and thereafter developed. Thereby, a trench pattern is formed by a photolithography technology.
As shown in FIG. 12C, by using the photo resist film 11 as a mask, the bottom anti-reflective coating 2 is anisotropically etched back by O2 plasma. In this case, a portion of the bottom anti-reflective coating 2 within the via hole 9 is etched away at least up to the level corresponding to the etching stopper film 5.
As shown in FIG. 13A, by using the photo resist 11 as a mask, the cap film 3 and the interlayer insulating film 4 are etched away and a wiring trench or groove 10 is formed.
Then, as shown in FIG. 13B, by using O2 plasma ashing and organic remover, the photo resist film 11 and the bottom anti-reflective coating 2 are removed.
As shown in FIG. 13C, the via hole 9 and the wiring trench 10 are filled with conductive material 12 such as Cu, and, by using a Chemical Mechanical Polishing (CMP) method, the surface of the cap film 3 is planarized. Thereby, all the conductive material 12 on the cap film 3 and almost all portion of the cap film 3 are removed, and a desired wiring structure is completed.
However, in the conventional method of forming wiring conductors mentioned above, it is necessary, in the process illustrated in FIG. 12C, to anisotropically etch back the bottom anti-reflective coating 2 made of organic material to a thickness of 300-600 nm. In such anisotropic etching back, it is difficult to precisely control the lateral size of the via hole and the like.
In order to solve such problem, there is known a method in which a via hole is not filled wholly with a material of a bottom anti-reflective coating but the via hole is partially filled with the material. That is, the via hole is not full-filled but partial-filled with the material of the bottom anti-reflective coating. With reference to the drawings, an explanation will be made on such method. FIGS. 14A-14C, FIGS. 15A-15C and FIGS. 16A-16C are cross sectional views each illustrating a structure of a workpiece during a process of fabricating a dual damascene structure according to such partially filling via-first dual damascene method. In these drawings, portions identical or corresponding to those in FIGS. 11A-11C, FIGS. 12A-12C and FIGS. 13A-13C used before for illustrating the above-mentioned fully filling method are designated by the same reference numerals, and detailed description thereof is omitted here.
First, as shown in FIG. 14A, on a lower wiring layer 8, an etching stopper film 7, an interlayer insulating film 6, an etching stopper film 5, an interlayer insulating film 4, and a cap film 3 are formed in this order. Then, a bottom anti-reflective coating (BARC) not shown in the drawing is applied on the cap film 3, and further a photo resist film not shown in the drawing is formed thereon. The photo resist film is then exposed by using KrF (krypton fluoride) excimer laser, and thereafter developed. Thereby, a via hole pattern is formed by a photolithography technology.
As shown in FIG. 14B, by using the photo resist film (not shown in the drawing) in which the via hole pattern is formed as a photo mask, the bottom anti-reflective coating (not shown in the drawing), the cap film 3, the interlayer insulating film 4, the etching stopper film 5 and the interlayer insulating film 6 are etched, thereby a via hole 9 reaching the etching stopper film 7 is formed. Thereafter, by using O2 plasma ashing or organic remover, the photo resist film and the bottom anti-reflective coating are removed.
Next, as shown in FIG. 14C, a bottom anti-reflective coating 2 made of organic material is applied on the cap film 3 and within the via hole 9. In this case, the bottom anti-reflective coating 2 is formed such that the via hole 9 is partially filled with the material of the bottom anti-reflective coating 2. That is, the via hole 9 is partial-filled with the material of the bottom anti-reflective coating 2.
As shown in FIG. 15A, a positive type photo resist material or film 11 is applied within the via hole 9 and on the bottom anti-reflective coating 2. In this case, the photo resist material 11 fills the space on the bottom anti-reflective coating 2 within the via hole 9.
Then, as shown in FIG. 15B, the photo resist film 11 is exposed by using KrF excimer laser, and thereafter developed. Thereby, a trench pattern is formed by a photolithography technology. In this case, a portion of the photo resist film 11 remains within the via hole 9.
As shown in FIG. 15C, by using the photo resist film 11 in which the trench pattern is formed as a mask, a portion of the bottom anti-reflective coating 2 on the cap film 3 is removed.
As shown in FIG. 16A, by using the photo resist film 11 as a mask, the cap film 3 and the interlayer insulating film 4 are etched away and a wiring trench or groove 10 is formed.
Then, as shown in FIG. 16B, by using O2 plasma ashing and organic remover, the photo resist film 11 and the bottom anti-reflective coating 2 are removed.
As shown in FIG. 16C, the via hole 9 and the wiring trench 10 are filled with conductive material 12. The conductive material is 12 is, for example, copper (Cu). Thereby, a via conductor or via 14 and a wiring conductor 15 are formed. By using a Chemical Mechanical Polishing (CMP) method, the surface of the cap film 3 is then planarized. Thereby, all of the conductive material 12 on the cap film 3 and almost all of the cap film 3 are removed by CMP, and a desired wiring structure is completed.
When forming the wiring structure according to the above-mentioned partial-filling method, it is possible to shorten a process of anisotropically etching back the bottom anti-reflective coating 2 by using O2 plasma removal described before in the process illustrated in FIG. 12C. Thereby, it is possible to suppress lateral expansion of the opening of the photo resist film 11 and to precisely control the lateral size thereof.
However, the above-mentioned conventional methods have the following problems. That is, in the method of forming a wiring structure according to the above-mentioned partial-filling technology, there is a problem that, in the process illustrated in FIG. 15C, a portion of the photo resist film 11 filling the via hole 9 does not melt away completely but partially remains within the via hole 9. This is because, laser light of the KrF excimer laser does not reach the portion of the photo resist film 11 within the via hole 9 sufficiently in the exposure process. The photo resist film 11 is made of positive type photo resist and, when exposed by the laser light, it becomes dissoluble in the developer. Therefore, if the photo resist film 11 is not exposed well by the laser light, the development rate in the developer does not become sufficiently high and the photo resist film 11 partially remains within the via hole 9.
On the other hand, in the process illustrated with reference to FIG. 14B, when the via hole 9 is formed by etching, a cross sectional area of an upper opening portion of the via hole 9 becomes larger than the cross sectional area of the bottom portion thereof, because of a characteristic of an etching behavior. Therefore, the side surface of the via hole 9 becomes slightly inclined such that an upper portion of the side surface warps backward or outside. Since the side surface of the via hole 9 is inclined, if the material of the photo resist film 11 buried in the via hole 9 remains, the cross sectional area of an upper portion of the remained material of the photo resist film 11 also becomes larger than a cross sectional area of a lower portion thereof, so that the side surface of the remained photo resist portion overhangs outside at upper portions.
Therefore, when, in the process illustrated in FIG. 16A, the cap film 3 and the interlayer insulating film 4 are etched, a portion of the material of the photo resist film 11 which overhangs outside becomes a mask for the interlayer insulating film 4 and the cap film 3. Therefore, an etching residue 13 of the interlayer insulating film 4 or the cap film 3 is produced just under the overhung portion. The etching residue 13 is formed so as to surround the opening portion of the via hole 9, and, therefore, is called a crown. The etching residue 13 can not be removed by the O2 ashing and the treatment by the organic remover which are performed for removing the photo resist film 11 and the bottom anti-reflective coating 2. Therefore, the etching residue 13 remains even after removing the photo resist film 11 and the bottom anti-reflective coating 2 by the O2 ashing and the treatment by the organic remover, and is buried within the conductive material portion 12. As a result, reliability of the fabricated wiring structure deteriorates.
In order to completely dissolve the material of the photo resist film 11 within the via hole 9, it is conceivable to make the development time longer than the conventional time. However, when the development time is made longer, the width of the wiring trench 10 becomes large, and it is difficult to form a minute wiring structure.
Therefore, it is an object of the present invention to provide a method of fabricating a multi-layer wiring structure which uses a dual damascene process and in which a minute wiring structure can be formed with high reliability and with high precision.
It is another object of the present invention to provide a method of fabricating a multi-layer wiring structure which uses a dual damascene process and in which etching residue surrounding each opening portion of a via hole is not produced and, therefore, a so-called crown is not formed.
It is still another object of the present invention to provide a method of fabricating a multi-layer wiring structure which uses a dual damascene process and in which the lateral size of each via hole can be easily and precisely controlled.
It is still another object of the present invention to obviate the disadvantages of the conventional method of fabricating a multi-layer wiring structure which uses a dual damascene process.
According to a first aspect of the present invention, there is provided a method of forming a wiring structure by using a dual damascene process comprising: forming a first interlayer insulating film on a lower conductive layer; forming a second interlayer insulating film on the first interlayer insulating film; forming a first photo resist film on the second interlayer insulating film, the first photo resist film having an opening for forming a via hole; etching the first and second interlayer insulating films by using the first photo resist film as a mask to form a via hole; forming an anti-reflective coating on the second interlayer insulating film such that a portion of the via hole is also filled with the material of the anti-reflective coating; forming a second photo resist film on the anti-reflective coating such that a remaining portion of the via hole is also filled with the material of the second photo resist film, a development rate of an exposed portion of the second photo resist film being 250-700 nm/second; exposing and developing the second photo resist film by using a photolithography technology and thereby forming an opening for forming a wiring trench in the second photo resist film; etching the anti-reflective coating and the second interlayer insulating film by using the second photo resist film as a mask to form a wiring trench; removing the second photo resist film and the anti-reflective coating; and filling the via hole and the wiring trench with a conductive material to form a via portion which is coupled with the lower conductive layer and a wiring conductor portion which is coupled with the via portion.
In this case, it is preferable that, in said etching the anti-reflective coating, the level of an upper surface of the anti-reflective coating in the via hole after etching is lower than the level of an upper surface of the first interlayer insulating film.
It is also preferable that a development rate of an unexposed portion of the second photo resist film is 0.05-0.4 nm/second.
It is further preferable that the second photo resist film is made of a methacrylate resist material, and the second photo resist film is exposed by using ArF excimer laser.
It is advantageous that the second photo resist film is made of an acetal photo resist material or an ESCAP resist material, and the second photo resist film is exposed by using KrF excimer laser.
It is also advantageous that the method further comprises, after said filling the via hole and the wiring trench with a conductive material to form a via portion and a wiring conductor portion, removing the conductive material on the second interlayer insulating film by CMP.
It is further advantageous that the method further comprises forming a first etching stopper film between the lower conductive layer and the first interlayer insulating film, and wherein, in said etching the first and second interlayer insulating films to form a via hole, said etching is stopped at the first etching stopper film.
It is preferable that the method further comprises forming a second etching stopper film between the first interlayer insulating film the second interlayer insulating film 6, and wherein, in said etching the second interlayer insulating films to form a wiring trench, said etching is stopped at the second etching stopper film.
It is also preferable that the first interlayer insulating film is formed of SiO2.
It is further preferable that the second interlayer insulating film is formed of at least one kind of materials selected from a group consisting of silicon oxide, ladder oxide, SiLK and SiOF.
It is advantageous that the conductive material is copper or copper alloy.
It is also advantageous that the lower conductor layer is a lower wiring layer.
It is further advantageous that the lower conductor layer is an electrode layer of a transistor formed on the surface of a substrate.
According to a second aspect of the present invention, there is provided a method of forming a wiring structure by using a dual damascene process comprising: forming a first interlayer insulating film on a lower conductive layer; forming a second interlayer insulating film on the first interlayer insulating film; forming a first photo resist film on the second interlayer insulating film, the first photo resist film having an opening for forming a via hole; etching the first and second interlayer insulating films by using the first photo resist film as a mask to form a via hole; forming a second photo resist film on the second photo resist film such that the via hole is also filled with the material of the second photo resist film, a development rate of an exposed portion of the second photo resist film being 250-700 nm/second; exposing and developing the second photo resist film by using a photolithography technology and thereby forming an opening for forming a wiring trench in the second photo resist film; etching the second interlayer insulating film by using the second photo resist film as a mask to form a wiring trench; removing the second photo resist film; and filling the via hole and the wiring trench with a conductive material to form a via portion which is coupled with the lower conductive layer and a wiring conductor portion which is coupled with the via portion.
In this case, it is preferable that a development rate of an unexposed portion of the second photo resist film is 0.05-0.4 nm/second.
It is also preferable that the second photo resist film is made of a methacrylate resist material, and the second photo resist film is exposed by using ArF excimer laser.
It is further preferable that the second photo resist film is made of an acetal photo resist material or an ESCAP resist material, and the second photo resist film is exposed by using KrF excimer laser.
It is advantageous that the method further comprises, after said filling the via hole and the wiring trench with a conductive material to form a via portion and a wiring conductor portion, removing the conductive material on the second interlayer insulating film by CMP.
It is also advantageous that the method further comprises forming a first etching stopper film between the lower conductive layer and the first interlayer insulating film, and wherein, in said etching the first and second interlayer insulating films to form a via hole, said etching is stopped at the first etching stopper film.
It is further advantageous that the method further comprises forming a second etching stopper film between the first interlayer insulating film the second interlayer insulating film 6, and wherein, in said etching the second interlayer insulating films to form a wiring trench, said etching is stopped at the second etching stopper film.
In the method of fabricating a multi-layer wiring structure which uses a dual damascene process according to the above-mentioned first aspect of the present invention, the development rate of the exposed portion of the second photo resist film is selected to become 250-700 nm/second. Thereby, when the second photo resist film is exposed, even if the light energy reaching the second photo resist film buried in the via hole is smaller than the light energy reaching the second photo resist film formed on the anti-reflective coating, the second photo resist film buried in the via hole can also be sufficiently dissolved in developer when the second photo resist film is developed thereafter. Therefore, it is possible to avoid insufficient dissolution of the material of the second photo resist film buried in the via hole. Thus, when the second interlayer insulating film is etched, it is possible to prevent etching residue from being produced. As a result, it is possible to greatly improve reliability of wiring. It is also possible to maintain rectangularity of the second photo resist film, that is, it is also possible to maintain a rectangular profile of each etched cross section of the second photo resist film. Further, according to the present invention, it is possible to shorten a time for an anisotropic etching back process of the anti-reflective coating portion buried in the via hole and, therefore, the lateral size of each opening of the second photo resist film can be controlled easily.
Also, when etching the anti-reflective coating, the level of an upper surface of the anti-reflective coating in the via hole after etching is lower than the level of an upper surface of the first interlayer insulating film. Therefore, when the second interlayer insulating film is etched, it is possible to effectively prevent etching residue from being produced due to the masking by an anti-reflective coating remained within a via hole.
In the method of fabricating a multi-layer wiring structure by using a dual damascene process according to the above-mentioned second aspect of the present invention, the development rate of the exposed portion of the second photo resist film is determined to be 250-700 nm/second. Thereby, when the second photo resist film is developed, the second photo resist film buried in the via hole can also be sufficiently dissolved in developer, while keeping the rectangular profile of the photo resist film. Therefore, it is possible to avoid occurrence of insufficient dissolution of the material of the second photo resist film buried in a via hole, and it is possible to prevent etching residue from being remained in the via hole. As a result, it is possible to greatly improve reliability of wiring. Further, since an anti-reflective coating is not formed, exposure light inputted into a via hole is reflected at the bottom portion of the second photo resist film buried into the via hole. Therefore, quantity of light reaching the second photo resist film buried in the via hole is increased and a development rate of the second photo resist film is increased. As a result, it is possible to surely prevent the second photo resist film from remaining undissolved.
Further, a development rate of an unexposed portion of the second photo resist film is selected to be 0.05-0.4 nm/second. Therefore, even when a quantity of exposed light energy inputted into the via hole is relatively small, it is possible to obtain sufficient development rate of the second photo resist film in developer, and it is possible to more surely prevent etching residue from being remained in the via hole. Also, it is possible to avoid missing of film material at unexposed portions of the second photo resist film and to improve rectangularity of profile of the second photo resist film.